This invention relates generally to microprocessor control systems, and more particularly to microprocessor control systems which include features, such as intermittent power-saving states. Such power-saving features may be of particular advantage, for example, in microprocessor-controlled equipment which is portable and which is intended to operate on self-contained power sources for extended periods of time.
Certain state-of-the-art portable microprocessor-controlled types of apparatus may operate in conjunction with static memory to retain application programs and operational states during times of shutdown. Retention of operational states may be particularly desirable for portable microprocessor-controlled apparatus. For certain rechargeable battery packs, a deep discharge is desired to prevent a loss of power storage capacity. Even if the portable apparatus operates on rechargeable battery packs, it is often considered more convenient from a user standpoint to be able to exchange a battery pack which has exhausted its charge for a fully charged battery pack, rather than to take time to recharge the battery pack which has exhausted its charge.
Static RAM devices, i.e., electronic memory devices which retain their memory cell states without refresh pulses, appear ideally suited to save application programs and microprocessor states during periods of a complete power-down condition of a microprocessor controlled apparatus. A retention of program and microprocessor states on power-down occurrences (for whatever the reason) further permits a user to resume operation, after subsequent power-up of a respective microprocessor controlled apparatus, just where the operation had been interrupted by the earlier power-down occurrence.
Unfortunately, static RAM devices are often considered, in an overall system perspective, to be comparatively costly and, moreover, the devices are also relatively large in physical size. The physical size of the memory devices in turn affects the physical size of apparatus that houses them. A resultingly relatively large unit is, however, less desirable than a comparatively smaller one when the units are intended to be handheld, as, for example, portable data collection terminals of an information retrieval system.
An alternative to using static RAM devices for saving application programs and microprocessor states during intermittent power-down states, is use of pseudo-static memory devices which are known as "PSRAM" devices. PSRAM devices require a refresh operation, very much like typical dynamic memory (DRAM) devices, often referred to as random access memory or simply as RAM devices. Thus, during normal operation, a memory management unit (MMU) periodically, for example at twelve microsecond intervals, addresses all locations of the memory with refresh pulses. Whenever an apparatus shutdown occurs, a controlling microprocessor (CPU) may cause the MMU to discontinue the application of refresh pulses. When the refresh pulses from the MMU no longer occur at the PSRAM, the PSRAM goes into what is referred to as a "self-refresh" mode. In the self-refresh mode, memory states of, or data within, the PSRAM are retained by internal refresh operations which require substantially less power than a continuation of refresh operations via the memory management unit (MMU).
A serious operational flaw occurs when a microprocessor device (CPU), which requires code access at the top of addressable RAM after a non-maskable interrupt, is sought to be operated in a memory environment consisting entirely of PSRAM devices. PSRAM devices, upon entering a data preserving self-refresh mode or state, become inaccessible to a CPU until they have been restored to a normal operating mode, in which mode the memory devices are refreshed by externally provided refresh pulses, such as by a MMU. In typical power-saving modes of operation, a respective CPU, such as an NEC V25, for example, is placed into a safe-stop state, which permits all operations to be shut down pending receipt of a non-maskable interrupt (NMI). The CPU, on receiving such an NMI "wake-up" signal, seeks to fetch a 4-byte address (referred to as a "vector") from an interrupt vector table (IVT) at the beginning of memory, which in a pseudo-static memory environment would be the PSRAM. Since the PSRAM at that time has not been placed into its normal operational mode, stored data may be lost, and the CPU may not be able to continue its operation.
Some computer systems use memory devices other than PSRAM in critical memory locations to be addressed by the microprocessor after shut-down. However, it appears to be desirable, among other reasons for simplicity sake, as well as from a standpoint of design considerations, to provide a microprocessor system with intermittent microprocessor shutdown states and with a capability of functioning in a memory environment of PSRAM devices.
Referring to FIG. 1, there is shown a microprocessor circuit which is designated generally by the numeral 10. A controlling circuit element of the microprocessor circuit 10 is a microprocessor device 12 which may be placed into a power-saving mode referred to as a sleep mode. As used herein, the term sleep mode refers to a shutdown mode of the microprocessor device 12, as distinguished from a stand-by mode, in which the microprocessor device 12 is not completely shut down, but operates in a slow, power-saving mode. The invention is described in reference to a microprocessor circuit which uses an "NEC V25" as a preferred example for implementing features of the invention. It is to be understood that other microprocessor devices may be used in implementing features of the invention and in achieving the advantages referred to herein. However, the V25 microprocessor device 12, depicted schematically in FIG. 1, has been found to satisfy adequately the requirements of implementing the invention as described herein.
In reference to both FIGS. 1 and 2, FIG. 2 relates to operations of the microprocessor device 12 of FIG. 1, wherein the microprocessor obtains operational data either from permanent memory, such as read-only memory 14 (ROM), or from static memory 15 (Static RAM). Both the ROM 14 and the Static RAM 15 are coupled in a known and typical manner to respective data and control ports of the microprocessor device 12 via a typical data and control bus 16, as shown by the "data and Control BUS" arrow and its coupling extensions labelled "B". Open arrowheads 17 and 18 identify the bus 16 as extending typically to further input-output ports and related microprocessor circuit elements or functional devices, such as disk drives or communications circuits coupled to respective ports. The use of these devices or circuits, also referred to as peripherals, is well-known in the art, but their selection is usually one of choice. Thus, the presence of selected peripherals is schematically shown by the respective arrows 17 and 18.
The microprocessor device 12 operates in a controlled sequence of operations as dictated by a control program found by selectively accessing memory locations of the ROM 14 and the Static RAM 15. The state of operations (or temporary wait periods) may be interrupted by signals appropriately referred to as "interrupts" or interrupt signals. An interrupt signal which requires action by the microprocessor device 12 is known as a "non-maskable interrupt" signal, or "NMI" signal. An NMI signal alerts the microprocessor device 12 to a) check for what type of interrupt signal has been received, and b) to perform an operation or to respond as prescribed by the control program when the presence of the particular type of interrupt signal has been indicated.
Two types of operations by the microprocessor device 12 are of interest in describing the invention. A first type of operation is a standard POWER-ON RESET. A power-on reset occurs typically on each start-up, typically a "cold start", when the power is first applied to the microprocessor circuit 10. All circuit devices or functional units coupled to and forming an integral part of the microprocessor circuit 10 are generally reset when power is first applied to them. This may be true, even though it may be desirable to then reload saved application program parameters into memory or other elements, so as to continue with an operation at a point at which the operation was interrupted prior to the most recent shut-down. To assure a "clean start", the power-on reset applied to the microprocessor device 12 is a logical "low" signal which is sustained for a period of "substantial" length following the application of power to the microprocessor circuit 10 to allow all circuit elements to be ready for operation before the clock signal triggers the microprocessor into action. Thus, system voltage (VCC) is applied to a reset port 21 of the microprocessor device 12 via an RC delay circuit 21 which has a time constant to generate, in the preferred example, a delay of 100 milliseconds. During the initial "power-on reset" period, the receipt of an non-maskable interrupt (NMI) signal is undesirable and might interfere with the proper reset operation. Consequently, an NMI signal input line 23 to an NMI port 24 of the microprocessor device 12 is AND-gated at an AND-gate 25 with an NMI holdoff RC delay circuit 26. The time constant of the RC delay circuit 26 is chosen to generate on start-up a time delay which blocks NMI signals for a time period following power-up of the circuit 10, causing an output of the AND-gate 25 (via signal line 27) to remain low during the period of the delay. In a preferred embodiment, the duration of the NMI holdoff is chosen to be 500 milliseconds, for example.
In a normal start-up of the microprocessor 10, to arrive at running an applications program, as shown by the "RUN PROGRAM" state 30 in FIG. 2, the microprocessor circuit 10 either follows a path via an "OFF" state 31 and a "POWER ON RESET" state 32, or from a "SAFE STOP" state 33 via a "WAKE-UP NMI" state 34. Except for an initial operation of the microprocessor circuit 10, a start-up via the "POWER ON RESET" state 32 also originates from the "SAFE STOP" state 33. A difference in the start-up procedure is that on a reset, the microprocessor 12 accesses the ROM memory locations 14, while on resuming operation after a WAKE-UP NMI 34, the microprocessor 12 jumps to an interrupt vector table which would typically be located at the lowest memory locations of the Static RAM memory 15.
While running a program, i.e., while being in the normal operational state 30, the microprocessor circuit 10 may be programmed to time out after a set time interval of non-interventive activity by an operator, for example after a period of one minute during which the microprocessor 12 has not received a keyboard entry NMI. A resulting time-out path to the "SAFE STOP" state 33 is shown by a direct path 35. Another path to the "SAFE STOP" state 33 is shown via a "SHUT-DOWN NMI" state 36. If the time-out timer for initiating a safe stop, or sleep mode, in the microprocessor 12 initiates a time-out NMI, the time out path 35 may be considered to be identical with the path via the "SHUT-DOWN NMI" state 36. A typical shut-down NMI, other than the time-out NMI, may be caused, for example, by a "low battery" indication. Another reason for the microprocessor 12 receiving a shut-down NMI 36 may be because of a sudden impending power loss, other than one caused by a steadily discharging battery. An indication of such a sudden power loss to the microprocessor circuit 10 may originate, for example, from a hardware safety switch coupled to a power pack compartment or connection. In all instances of receiving a time-out 35 or shut-down NMI 36, the microprocessor circuit 10 would be instructed to stop operating in any applications program and immediately store all, then current, operating parameters in, for example, separately battery-backed memory, or other non-volatile memory for future recall. Any start-up after reaching the "SAFE STOP" state 33, be it via the "POWER ON RESET" 32 or via the "WAKE-UP NMI" 34 permits a user to restore the most recent state of operation of the microprocessor circuit 10, thus, resume operations where they had been left off prior to the microprocessor 12 entering the sleep mode. Use of the above-described power-saving sleep mode operation presupposes the presence of non-volatile memory for storing all necessary operating parameters while the microprocessor is in the sleep mode. Moreover, it presupposes ready accessibility of such non-volatile memory to recall the operating parameters when resumption of operations by the microprocessor 12 is called for.
Since pseudo-static RAM memory requires to be re-activated from its self-refresh mode before it may and can be accessed by a microprocessor to retrieve or store data, the use of pseudo-static RAM memory in place of the Static RAM memory 15 as described with respect to FIG. 1 has been found to present operational problems.